Modular memory array systems known in the art are configured by organizing banks of appropriately sized memory chips. Such systems are typically comprised of multiple banks of memory having shared access over a connector or other restricted interconnect system, i.e. finite bandwidth busses. For instance, sixteen 16M.times.4 Dynamic Random Access Memory (DRAM) chips can be organized to give one bank of 128 megabytes of memory that is 64 bits wide and 16 megabytes deep. Typically, in order to get more (i.e. deeper) memory, more banks of the same size are added with the same word size (width). Addressing of memory within a particular bank normally involves coding (and decoding) particular bits of the memory address bus to indicate a selected bank. That is, in order to access a selected bank of the multiple banks of shared memory, the particular bank to be accessed is determined by decoding certain bits of the memory system address bus. For example, in a multi-bank system with 4 banks of 128 megabytes of memory per bank that is 64 bits wide and 16 megabytes deep, the memory address bus can be coded as follows: the first twelve bits of the address bus (A[11:00]) are the DRAM column address; the next twelve bits (A[12:23]) are the DRAM row address; and the last two bits (A[25:24]) are the bank select bits. The bank select is usually implemented such that only the selected bank's control lines will be active, i.e., control line signals will not be driven to every bank. Thus only one bank is accessed at one time.
One known type of modular memory array system, illustrated in FIG. 1A, has the memory address distributed by a single buffering mechanism. Bank selection of one of the banks (bank 0, bank 1 . . . bank N), is accomplished by unique control signals mutually exclusively issued to the respective bank being selected. In the system illustrated in FIG. 1A, three control signals are sent to a control buffer 20, but the three signals are sent via the buffer 20 only to the bank being selected (although three signal lines are routed between the control buffer 20 and the memory banks, only one control line is shown for simplicity in the drawing).
In this known implementation, address lines (again only one shown for simplicity), are buffered by an address buffer 22 such that the same (logical) copy is routed to each bank. Accordingly, toggling memory addresses are seen at each of the memory banks whether the bank is being selected or not, which results in increased switching noise. Other problems result, in that for systems with a significant number of banks, high-current drivers and/or multiple (physical) copies of the address may have to be used to drive the address lines which are always driven to every bank (unlike the control lines). Disadvantageously, power consumption on the memory array is greater, and/or physical space requirements for driving the memory address are increased.
Another known modular memory array system implementation is illustrated in FIG. 1B. In this implementation a unique copy of the address is distributed from a port controller 24, through an address buffer 26 to the selected bank, so that switching occurs only at the address of the bank being accessed. This scheme has the advantage of reduced switching noise and power consumption on the memory array. Major disadvantages, however, are associated with the requirement for issuing a unique address to the address buffer for each memory bank. On a memory array accessed over a connector, like a daughter card system, the input/output (I/O) requirements of the connector increase. Worse still, is the fact that the I/O requirements (i.e. pin out) of the driving port, usually an application specific integrated circuit (ASIC), increase proportionately. Further, greater amounts of physical space on the memory array card are required to accommodate the increased I/O requirements.
In all DRAM memory array implementations, the memory chips must be accessed periodically to refresh the information stored in the DRAMs. Refresh operations, if not optimized in terms of timing and duration, may negatively impact memory system bandwidth. Refresh operations also require significant amounts of power to cycle through the DRAM memory bank(s), adding to the power requirements of the memory array. Known refresh schemes themselves can introduce noise in the system as a result of current surges that occur during transition times in the refresh cycle. In-rush current surges can cause "ground-bounce" which can lead to spurious data corruption and/or loss of data. In large memory arrays refresh currents are significant and can account for a major portion of the DRAM power dissipation. Significantly higher power consumption can lead to the need to use larger, higher power components, and may, introduce difficulties associated with heat buildup in and around the memory array.